-------------------------------------------------------------------------------
-- Title      : Interval based tick generator
-- Project    : 
-------------------------------------------------------------------------------
-- File       : tickGen.vhd
-- Author     : Paul W
-- Company    : 
-- Created    : 2012-09-30
-- Last update: 2012-12-11
-- Platform   : 
-- Standard   : VHDL'93
-------------------------------------------------------------------------------
-- Description: Generate a tick based on the generic clk tick INTERVAL
-------------------------------------------------------------------------------
-- Copyright (c) 2012 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2012-09-30  1.0      paul	Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

package tickGen_CMP is
  component tickGen is
    generic (
      INTERVAL : integer);
    port (
      in_clk   : in  std_logic;
      in_en    : in  std_logic;
      out_tick : out std_logic);
  end component tickGen;
end package tickGen_CMP;

library ieee;
use ieee.std_logic_1164.all;

entity tickGen is
  
  generic (
    INTERVAL : integer := 50000);

  port (
    in_clk   : in  std_logic;
    in_en    : in  std_logic;
    out_tick : out std_logic);

end entity tickGen;

architecture rtl of tickGen is

  signal cnt     : natural range 0 to INTERVAL;

begin  -- architecture rtl

  -- Output a tick every time we reach the INTERVAL with continuous enable
  counter_proc : process (in_clk) is
  begin  -- process counter_proc
    if rising_edge(in_clk) then      -- rising clock edge
      out_tick <= '0';
      if in_en = '1' then
        cnt <= cnt + 1;
        if cnt = INTERVAL-1 then
          cnt      <= 0;
          out_tick <= '1';
        end if;
      else
        cnt <= 0;
      end if;
    end if;
  end process counter_proc;

end architecture rtl;
